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DFT questions about flip flops

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cooldude040

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In scan chains if some flip flops are + triggered and remaining flip flops are -ve triggered what happens??????????

In multiple clock domains we use lock up latch what about the above question?
 

visualart

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DFT questions

u may part them in disperate clock domain. use the anothe clock chain.
 

dft_guy

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Re: DFT questions

For designs with both positive and negative clocked flops, the scan insertion tool will always route the scan chain so that the negative clocked flops come before the positive edge flops in the chain - this way no lockup latch is needed.

However, the concern is during capture mode, and what feeds into those negative edge flops - in many cases, it's positive clocked logic, or, as you say, another clock domain. In the case of posedge flops from the same clock domain, the negedge flops will always capture the data just captured into the posedge flops on the posedge of the clock, so the ATPG has to work a little harder to get the fault coverage, but it's not a big deal.

For data traveling between clock domains, it all depends upon how the clock trees are balanced (if they are at all). If the clock domains are completely asynchronous, you just have to handle it in the ATPG (mask the receiving flops, essentially).

John
DFT Digest
DFT Forum
 

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