DFT question in multi clock domain and lockuo latch

[ericyuan]

dft internal_clock

how to handle DFT methodology when there are many different clock domain(different frequency), and the lockup latch with STA methodology, and some test issues.


Thanks a lot

 

[stormwolf]

What you want to do ? stuck-at or transition?
If stuck-at , you don't need to mind about frequent.
if transition, you need to read some paper about onchip clock.

 

[manu_leo]

If u have multiple clks, you will have lock up latches inserted at the boundary clk domains.
The EDA tool u r using shd take care of this

 

[shiv_emf]

if u hav multiple clocks n u want only single SCAN chain ...then use set_scan_configuration -mix_internal_clock
i am nt sure abt option but ... U can do tht ..

if u want separate scan chains for different clock domain ..use -internal_clock multi
Shiv

 

[naveenkrishnan]

The most safe option is to have single scan clock. Insert muxes in clock path and use scan mode signal to select an external controllable clock in scan mode.

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