htt830105
Newbie
Hi Seniors,
I use TMAX/VCS to do ATPG/Simulation, in which the MAX Testbench is performed.
The Chain/Serial10/Parallel simulation are used as sign-off cases as well.
I know how to do it, but to get a better understanding, I list some questions in the following, plz
1. Can anyone explain "parallel simulation" in advanced? (Yeap, I know parallel simulation means forcing shift value to register directly by simulator, and then measure it)
But it's abstract, can u explain it by using "waveform" or "protocol" format plus circuit?
2. What's the meaning of "parallel scan load" shown in simulation log file?
3. What's "n-shift" in parallel pattern? Why we need this? Can u explain it by using some chart with timing concept?
4. Where is the "forcing" procedure in maxtestbench? Since Max Testbench often confused me. If u can explain Max Testbench more detail, it's better.
5. Plz provide some useful materials related to these questions if u can. Many thanks!
Regards,
I use TMAX/VCS to do ATPG/Simulation, in which the MAX Testbench is performed.
The Chain/Serial10/Parallel simulation are used as sign-off cases as well.
I know how to do it, but to get a better understanding, I list some questions in the following, plz
1. Can anyone explain "parallel simulation" in advanced? (Yeap, I know parallel simulation means forcing shift value to register directly by simulator, and then measure it)
But it's abstract, can u explain it by using "waveform" or "protocol" format plus circuit?
2. What's the meaning of "parallel scan load" shown in simulation log file?
3. What's "n-shift" in parallel pattern? Why we need this? Can u explain it by using some chart with timing concept?
4. Where is the "forcing" procedure in maxtestbench? Since Max Testbench often confused me. If u can explain Max Testbench more detail, it's better.
5. Plz provide some useful materials related to these questions if u can. Many thanks!
Regards,
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