DFT parallel pattern simulation mismatch analysis

Status
Not open for further replies.
V

Vignesh_J

Newbie level 6
Joined
Jan 8, 2019
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
100
Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI

Kindly correct me if I am wrong in this part.
For parallel pattern simulation, the values are forced in D pin of FF's by the simulator
 

For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
What you should trace back is the clock , time it lanuch in the shift window and double check in your procedure

Tiep Ngo
 
Last edited:
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…