Hi,
In genneral, DFT Implemenation is to insert a DFT circuit upon a gate level design.
This step including:
- Convert normal Flops to Scan-Flops. ( in some special cases, a Flops could be non-scan one )
- Connect those Scan-Flops into number of chains, called scan-chain.
The number of scan-chain and the number of Flop per scan-chain will be depends on Test technique/EDA that you want to apply.
- Number of scan-chain normally very huge comapre with design Port, hence, they are compressed and decompressed. This logic also inserted by some DFT EDA tools.
- To control the operation of DFT, a control logic also be insert to origial gate level design. It works in Test mode only.
DFT verification:
- Verify the correctness in function of Flops and Standard cells via scan patterns.
- Pattern will be genarated by EDA tool automatically. Patterns will be shifted into scan-chain.
- Capture the output of scan-chain and compare with expected value.
- The pattern then will be used to check on silicon device after fabrication. We can eliminate the fail one here.