I am working on ATPG using cadence encounter test, getting low coverage for transition faults( at speed) . the tool reported the warnings but these warnings are not affecting the low coverage.
Can anyone help me how to dig further to find which part of the logic is not tested? how to improve the coverage
I am working on ATPG using cadence encounter test, getting low coverage for transition faults( at speed) . the tool reported the warnings but these warnings are not affecting the low coverage.
Can anyone help me how to dig further to find which part of the logic is not tested? how to improve the coverage
Dump all the atpg untested faults and check, which module is having more faults then check whetehr the clock is propogating to that particular module properly or not.
What is the coverage number you are getting?