[DFT] how to deal with the constant 0 or 1 cells

[remandow]

hello friends:
how to deal with the cells which are constant 0 or 1? i find the D pin of these cells is connected to the logic0 or logic1. and these cells are not included in a scan chain. how to deal with. who can help me.

---------- Post added at 16:16 ---------- Previous post was at 14:40 ----------

someone can help me to fix it?
thanks a lot!

 

[morris_mano]

how to deal with the cells which are constant 0 or 1? i find the D pin of these cells is connected to the logic0 or logic1. and these cells are not included in a scan chain. how to deal with. who can help me.

Why are those flops not included in the scan chain? If you include them in a scan chain, you will be able to drive the combo logic with scan data loaded into this flop and get more coverage.

 

[remandow]

Why are those flops not included in the scan chain? If you include them in a scan chain, you will be able to drive the combo logic with scan data loaded into this flop and get more coverage.

These violations happen when i executive command dft_drc after insert_dft. And i check them with schematic i find that these DFFs' D pin are connected to logic 0 or logic 1. I am not sure about why these DFFs are not included in the scan chain. I think it doesn't matter whatever the input of the D pin of the DFF is when a chip is under test mode. So i just want to fix it and include them in a scan chain. But i don't know how to do it.

 

[morris_mano]

If the flop you are mentioning is getting test clock and is a scannable flops, I don't see a reason why it would not be included in scan chain. First check after insert_dft whether those flops are scannable. You could check if that flop has pin like SI, SE. If you could post your violation report, that would give more information on your issue?

 

[remandow]

This picture will show some information about my issue. The violation is described as "Cell is constant 0". We can see that those flops are not scannable after insert_dft. The pin TI TE also connect to logic 0. I also check the test clock of those flops and find that the test clock has no problem.
The picture above is created by the Design Vision's (Synopsys) ViolationBrowser window.
When I check the man page of this violation. It tells me do like this:
Validate the condition that results in the output of the cell being constant. If this is intentional, the violation can be ignored. If not fix the condition. Cells with constant outputs will not be autofixed.
I am not sure how to fix it.

 

[remandow]

Should I fix this kind of violation?And why?