dft requirements bist
Hi Jaydip,
Points to note..
No need of inserting scan chain to your memory core.
You can bypass the memory at the RTL stage itself and make your design test friendly. (or)
You can bypass the memory by inserting the testpoints around it by using the eda tools.
Both MBIST and SCAN tests will not run simultaniously.
Beusure of the MBIST logic test ports are accessable to the test equipment. I mean, you need to control your MBIST core from outside and can observe the results.
You can plan the test architecture accordingly and so, u can either use different test potrs or can multiplex ur ports for testing of scan and MBIST.
Rest will be followed during the course of ur work.
Good Luck..
Hope this will help
For more info..
**broken link removed**
- sunil budumuru