DFT - Design for Testability

[meet81193]

Can we apply pattern generated in ATPG for Stuck fault to IDDq fault or Transition Fault?

If yes, when can we do it? Is it beneficial? Is any extra condition needed for it?

If no, why can't we apply it? What should we do to make it applicable?

Please be as brief as possible. Also provide is you got any ref.

Thank you, in advance

 

[maulin sheth]

Yes. You can apply Stuck-At patterns for IDDQ but you can not apply Stuck-At patterns to Transition.
In transition fault, we have to do transition in the same pattern. Its generally like : Scan - in, launch(launching the transition), capture and shift out where in stuck-at shift-in,capture and shift-out only.

To use Stuck at as a IDDQ is not simple task, because in IDDQ we are measuring current at the VDD/VSS pins. But Stuck-at patterns are measuring the voltage at Scan out pins. We have to do conversion.
2nd thing is that , generally design have a high stuck at pattern count but all can not apply for IDDQ. So we have to do select some patterns for IDDQ from so many stuck at patterns.

Regards,
Maulin