Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DFT Compiler , problem with report_fault

Status
Not open for further replies.

animotion

Junior Member level 1
Joined
Aug 22, 2009
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Ireland
Activity points
1,428
All,

I am working with DFT Compiler to insert a scan chain to a digital design.
After the scan insertion, the coverage is very small and I have used "report_fault" to find the parts of the design that have lowest coverage.

I am gettgin back:
Error: The CTL mode does not include valid patino.

Presumable a CTL model is written at some point in the flow and it does not have enough/correct information.

1)What commands cause a CTL model to be written?
2)Does anybody have any further information beyond that which the Design Compiler man pages gives me?

Regards
animotion
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top