DFT - chian pattern failure

[abc_81]

Hi,
Please help me in understanding the following,
How to debug chain test failure ? How to find the failure flop for chain test patterns?
What is the pattern used for chain test ? is it specific to the tool or can it be same for all ?

Thanks
Viayalakshmi

 

[rca]

The first pattern of the vector does not have any clock capture to just shift in shift out, and by this check the scna chain continuity and the ATE to chip connections.
1- do you have a fail in simulation?
2- is it a a general question?

 

[abc_81]

Thanks for the response.
Simulation is actually failing , so I have run pareallel simulation with post_shift=5 option in mgc tool.

 

[rca]

1-
the fail occurs during the first patterns?
usually the testbench generated by tools like fastscan or tetramax indicate which flop has the wrong value.
2-
did you run also the serial simulation?

 

[abc_81]

I have used serial testbench for the chain pattern. With this simulation is failing. To debug this I have run parallel simulation with post_shift to idendify the failing flop. Is it the right approach ?

 

[rca]

personnaly, I prefer to work only in serial mode.
parallel, will confirm the model of std between verilog and atpg are equivalent and the macro models are also align, then the patterns will be good, I expect the ATPG generate good patterns because models are good as well.

In serial mode, the timing could have "bigger" impact.
To debug, i check there is not timing check reported.
no X from macro models propagated.
scan signals clean (clock, shift/capture, scan in, reset)
primary inputs defined during capture.