Devide frequency into 3 using AHDL or Verilog HDL

[ThaiHoa]

If i want to get 8.33MHz frequency from 25MHz frequency, how can i do when I'm using AHDL or Verilog HDL

 

[salamander]

Hi,
simply an @always posedge clock block where you count an reg from 0 to 2 an then toggle clock_slow (clock_slow=~clock_slow).

Now you can use clock_slow as your 8Mhz Clock...

regards
salamander

 

[davorin]

Hi,
simply an @always posedge clock block where you count an reg from 0 to 2 an then toggle clock_slow (clock_slow=~clock_slow).

Now you can use clock_slow as your 8Mhz Clock...

...which isn't 8.33MHz at all but input frequency/6 (o;


...and if you weren't too lazy searching here in this forum you would have come up easily with:

// Divide by 3 module
//

module divide(
	CLK,
	DIV3
);

	input	CLK;
	output	DIV3;

	reg	cnt_a, cnt_b;
	
	always @ (posedge CLK)
	begin
		cnt_a <= ~cnt_a & ~cnt_b;
		
		cnt_b <= cnt_a;
	end

	assign	DIV3 = cnt_b;

endmodule

 

[hock]

xilinx has a application noet on it.
u can generate many odd freq using it.
hock

 

[Black Jack]

I`m sorry for mistake

Clock Divider with 50/50 Duty

 

[★jerome&#97]

why not to decompression the file-Ndiv_v1.zip.

 

[dragon_boat]

who can decompress the file?
i use winrar3.

 

[karlheinz]

I used 7zip (www.7zip.org) to decompress, Winzip reported an error in the archive.

 

[Arthurzss]

I use winzip 9.0, and it can decompress it.

 

[mc_navman]

If you want to get any given frequency from a source you can use DDS (Direct Digital Synthisis.) That is if you dont have a PLL already. I assume that you are using Altera parts as you mention AHDL if you have a cyclone then there should be some PLLs on board so problem solved.
DDS has the problem of phase jitter these numbers would have some serious jitter problems I think.

 

[silencer3]

there is a pdf fine from st micro-electronics. That is an excellent note on how to divide clock with 50% duty cycle and you can divide with odd numbers also. search net for pdf file st clock divider. this is patented one.

 

[Black Jack]

there is a pdf fine from st micro-electronics. That is an excellent note on how to divide clock with 50% duty cycle and you can divide with odd numbers also. search net for pdf file st clock divider. this is patented one.

Where PDF :?:

 

[silencer3]

Here are two pdf files for unusual clock dividers : excellen

download the tar file and install. you get two pdf files giving excellent clock dividing methods


enjoy