determining latency in clocks

[prsk]

How many D flip flops do you require to determine the latency of N clocks (assume inverters are available for free) ?

 

[prassingh]

I'm not sure what actually you want to find out. But latency is generally seen on full clock path (from source of clock {generally pll or pads} to clock end-point {flops or pads}) . So once you have full path you can just use up delays specified in libs and compute latency {should use PT for it}

 

[mutant_corpse]

That is an ambiguous question. I think you mean something else. Latency can be computed by any timing tool, or you can also see it in the timing path. For detailed info: refer https://vlsi-soc.blogspot.in/2013/04/clock-jargon-important-terms.html