manofwax
Junior Member level 1
Dear All,
I want to stop my counter when clk1 and clk2 are coincidence.//rising edge of them happen at the same time...
The freq of clk1 = 100MHz
The Freq of clk2 = 100MHz * 16/17
Rising edge of clk1 and clk2 should eventually align together at the 16th cycle of clk1 and 17th cycle of clk2 assuming they started at the same time in the beginning.
But i can't detect this event. Here's my code:
entity counter is
generic(n: natural := 8 );
port(clock1 : in std_logic;
clock2 : in std_logic;
count : in std_logic;
Q ut std_logic_vector(n-1 downto 0));
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0) := "00000000";
signal stop : std_logic := '0';
begin
process(clock1, clock2)
begin
if (clock = '1' and clock'event) then
if count = '1' and stop = '0' then
Pre_Q <= Pre_Q + 1;
end if;
if ((clock_ref = '1' and clock_ref'event)) then
stop <= '1';
end if;
end if;
end process;
Q <= Pre_Q;
end behv;
Thanks in advance...
I want to stop my counter when clk1 and clk2 are coincidence.//rising edge of them happen at the same time...
The freq of clk1 = 100MHz
The Freq of clk2 = 100MHz * 16/17
Rising edge of clk1 and clk2 should eventually align together at the 16th cycle of clk1 and 17th cycle of clk2 assuming they started at the same time in the beginning.
But i can't detect this event. Here's my code:
entity counter is
generic(n: natural := 8 );
port(clock1 : in std_logic;
clock2 : in std_logic;
count : in std_logic;
Q ut std_logic_vector(n-1 downto 0));
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0) := "00000000";
signal stop : std_logic := '0';
begin
process(clock1, clock2)
begin
if (clock = '1' and clock'event) then
if count = '1' and stop = '0' then
Pre_Q <= Pre_Q + 1;
end if;
if ((clock_ref = '1' and clock_ref'event)) then
stop <= '1';
end if;
end if;
end process;
Q <= Pre_Q;
end behv;
Thanks in advance...