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Spare cells are logic gatesthat arw added to a design to allow quick logic changes to be made without a replacement of the chp . in other terms witout completer reroute, these cells can be used to ECO changes.
Spare cells we are adding as an Extra cells for future use. Spare cells will be having some logics with them like logic gates and flops. The clock nets also routed to the spare cells and CTS also done. At the end of your design process if the design engineer add some logics with your chip you cannt start the backend process from the beginning, at that point these spare cells will be utilized by doing ECO.
Does it have Vdd and Vss connectivity?? to the spare cells?
How do u decide that this particular space is allocated for spare cells??
and does it go through the routing stages?? If it goes then there might be a tming problem right??
When these spare cells are placed?? at the time of floorplanning ??
Will these spare cells be there in verilog netlist???
I have checked the verilog netist its not there.........But i have seen filler cells in verilog netlist but not spare cells y so ?
spare cells are the cells by which u can implement any type of logic with some amount limitations.for spare cells we will connect clocks and power but we will not connect the o/p of spare cells and input of spare cells to any net. such that when we want to implement any chage in the manufactured chip we can implement by doing fibbing.whcih is nothing but cutting metal layer using laser and connecting the new metal layer to tthe required cell. for this purpose people will put extra spare cells at each module according to the importance of the module in the chip.
can u please tell me that whether it will be there in verilog netlist ??? before importing our design ??
And if it is there then by wt name it will be there?
And at the time of doing floorplan will it be available??
Added after 3 minutes:
And we have to allocate some space for the spare cells right for the further use.... So how do we know that we are going to allocate...for that use only bcz the space will be left over for the decap cells to stabilize the power between vdd adn vss) , filler cells( to have a continuity in Nwell and follow pin right) and well tap cells( betwwen rows ) and end cap cells( at the row sites right?) so where is the space for the spare cells???????????????? Plz explain in detail as much as u can
SOC Encounter has the ability to insert spare cells if you want it to. You give it a list of cells (which flip-flops and gates) you want it to insert, a number or percentage of total cells that you want to be spare, as well as stride/offset locations and it will insert it. The verilog netlist you export from Encounter after placement will then include spare cells.
Alternatively, you can go into the verilog netlist (post-synthesis) and insert them yourself by simply instantiating cells that are connected to logical 0 (or 1) with their output pins left floating.
By default there will be no spare cells in the netlist. But for ECO purposes, some netlists do have spare cells present within them. If the netlist has sparecells, their inputs would be tied to either 0 or 1 (or to the respective clock in case the spare cell is a flop)
But spare cells can also be inserted at the top level depending on the nature and kind of the logic. When inserted on the top level, the spare cell inputs must be tied to 0 or 1.
When we want to change the cell or to upsize or downsize we go for ECO right? so does ECO has the spare cells?? I have seen some cells there named as BUFFX1,BUFFX2 , and so on
plz let me know
spare cells are used for ECOs. some cells are marked as spare during normal design flow and they are sprinkled all around the die so that they can be used if any minor changes in designs occur- thats what is called ECO in simple words. so ECOs dont have spare cells but they can use spare cells to realize the functionalities
my 2 cents about the discussion about spare-cells.
In order to address the last minute changes or need to fix any functional or any timing changes we go for a stage called as ECO[Engineering Change Order].
So at this stage we use the free cells or spare cells during Metal only Fixes.
so what this spare -cells ?
By the name calls these are some extra cells dumped in the chip to help us in order to honour ECO's.
What is the metric or amount of spare-cells to be used?
There is no hard and fast rules , it is totally based on the confidence level of the design as well as the quality of the test-vectors, usuallly around 5% spare-cells will be used as extra cells.
Whether spare-cells will be used in RTL or during implementation stage[place and route]?
Spare-cells could be used in RTL stages manually instantiate a spare-cell modules which has the flavour of the spare-cells.
Or
Use it in the implementation stages, say it in place and route stage now a days placement tools are clever in this concept of spare-cells insertion.
What is the flow i should use RTL spare-cells or implementation based , please guide me.
Using RTL based there is a limitation, that all the cells will be cluttered in a same place and distribution of the cells will not be honoured.
where as in the implementation based the distribution can behonoured.
what should i do with the input of these spare-cells.
The input of these spare-cells need to be tied to zero and not let floating this is very very important otherwise will lead to lot of leakage current which is dangerous for the chip.
What are the flavours of cells i should use for spare-cells.
Usually few flops,buffers,inverters,latch,few clock-gating cells,nor,nand.
how do i ensure that the spare-cells are distributed.
divide the chip in to many rectangles and specify the sparecells in each rectangles so that the distribution of the spare-cells could be controlled and honored.
should i built tree for spare-cell flops as well up front.
you can do this , and this is better, so that in case in future if you want to opt for this flip -flop for ECO then it would be better and you dont want to think on clock-tree balancing of this flip-flop.
hope this answers few doubts and clear the concepts.
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