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designing LUT using VHDL - please help

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shreeharshakg

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designing LUT using VHDL

Hi,

Sir, i am designing DA-FIR filter using sysgen. now i have designed FIR filter and i am getting the coefficient values. they are real numbers, eg: 0.27655, -0.0976,...... now i want to design an LUT which should do the following :



* address is 0 to 15, 4-bit and let the coefficients be w0,w1,w2,w3. w0->0.273, w1-> -0.093, w2->0.093, w3-> -0.273 .

* for a3a2a1a0

0 0 0 0 -> 0

0 0 0 1 -> w0

0 0 1 0 -> w1

0 0 1 1 -> w1+w0

0 1 0 0 -> w2

.......



* in the above shown way, depending on the bit set , it must add/subtract the coefficients and store the results.

* here i'm finding difficult in add/sub of real numbers and converting it into bits.



- how can this be done using VHDL code.. can you please help me in getting through this.





thanking you sir,



yours sincerely,

Shree.
 

Look at Active HDL,
try in it TOOLS -> IP Core Generator -> PDA FIR core with any parameters,
and it generates you a VHDL code with such a LUT coding.
 

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