I've been thinking a lot on this. My lecturer explained the CMOS implementation of NAND and NOR and NOT but that was only using the switch model. But i was wondering how to design the circuit if it is a bigger function say AB'+A'B or something like that. I need a logical process through which i can design a CMOS circuit given a boolean function. Can someone help me? Please help...
You would have to design PUN (Pull Up Network) and PDN (Pull Down Network) expressions from the logic function. Remember thatn PDN and PUN are the duals of each other e.g.
Dual of AB'+A'B is
(A'+B).(A+B')
where the former one will form PDN while the later one PUN.
You would have to design PUN (Pull Up Network) and PDN (Pull Down Network) expressions from the logic function. Remember thatn PDN and PUN are the duals of each other e.g.
Dual of AB'+A'B is
(A'+B).(A+B')
where the former one will form PDN while the later one PUN.