But it requires a very big shift register and a very big comparator!You don't use an N-state FSM you would use an N-bit shift register and an N-bit compare, when the shift register contents match the sequence then the sequence has been found.
Rtl for shift reg and comparator are simple when the size of them are small. For a big shift reg and big comparator it will be come tedious to write such an RTL with same kind is assignment statements in the shift reg RTL. Do you have any way to reduce the tedious work of writing RTL for shift reg?Hi,
Answered in post#4.
Any usual hardware description language will do, Some tools even support schematic input.
But in this case VHDL or VERILOG code is really simple.
Do a search for "shift register" and "comparator"..
Klaus
I suppose it's one line of code. Writing the literal representing the compare value is most of the work.Rtl for shift reg and comparator are simple when the size of them are small. For a big shift reg and big comparator it will be come tedious to write such an RTL with same kind is assignment statements in the shift reg RTL. Do you have any way to reduce the tedious work of writing RTL for shift reg?
By repeating the same Q again and again, I think the OP wants us the write the code for him! ;-)Rtl for shift reg and comparator are simple when the size of them are small. For a big shift reg and big comparator it will be come tedious to write such an RTL with same kind is assignment statements in the shift reg RTL. Do you have any way to reduce the tedious work of writing RTL for shift reg?
Why don't you begin coding your RTL with 10 digits (this 10 can be a generic value, changeable from the top-level module) and then expand it to 50 or 100. During coding identify the signals which has to be scalable. Show us what you have done and you can get more help.How can we design such FSM in hand if the sequence has more number of digits and it is as much as 50 digits or 100 digits?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 input Din, clk, reset; Output reg Dout; reg Shreg[99:0]; always@(posesge clk) begin If (!reset) Shreg<= 0; else for (i=0, i<100, i=i+1) Shreg[i]<= Shreg[i-1]; Shreg[0]<= Din; Dout<= Shreg[99]; end
for (i = 1, i < 100, i = i+1)
Shreg[i] <= Shreg[i-1];
the code length doesn't change with operand size. remember, you should be writing RTL, not schematic or any form of structural code. R T L.Rtl for shift reg and comparator are simple when the size of them are small. For a big shift reg and big comparator it will be come tedious to write such an RTL with same kind is assignment statements in the shift reg RTL. Do you have any way to reduce the tedious work of writing RTL for shift reg?
Code Verilog - [expand] 1 2 3 4 5 // one liner N-bit shift register (left shift) always @(posedge clk) shift[N-1:0] <= {shift[N-2:0], din}; // the compare always @(posedge clk) match <= (shift == N_BIT_CMPR_VALUE) ? 1'b1 : 1'b0;
Should this not be, below ( your example accesses Shreg[-1 ] which
is an unknown / illegitimate value). Even though you corrected for this
with Din assignment to Shreg[0].....Just better programming to keep
indexes correct.
Code:for (i = 1, i < 100, i = i+1) Shreg[i] <= Shreg[i-1];
I am a C embedded programmer trying to learn Verilog. So I am writing@fragnen Sigh, Learn how to write RTL.
Code Verilog - [expand] 1 2 3 4 5 // one liner N-bit shift register (left shift) always @(posedge clk) shift[N-1:0] <= {shift[N-2:0], din}; // the compare always @(posedge clk) match <= (shift == N_BIT_CMPR_VALUE) ? 1'b1 : 1'b0;
There I wrote the code for you.
So many people come onto this site and post code that looks just like a software translation of a shift, when the hardwarecentric way of doing it is so much easier to write and understand.
Code Verilog - [expand] 1 always @(posedge clk) Q <= D;
Code VHDL - [expand] 1 2 3 4 5 6 process (clk) begin if rising_edge(clk) then Q <= D; end end process;
Code Verilog - [expand] 1 2 3 shift_reg[2] <= shift_reg[1]; shift_reg[1] <= shift_reg[0]; shift_reg[0] <= din
Code Verilog - [expand] 1 2 3 shift_reg[2:0] <= {shift_reg[1], shift_reg[0], din}; // or simply shift_reg[2:0] <= {shift_reg[1:0], din};
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