Jun 5, 2003 #1 A Aircraft Maniac Member level 5 Joined May 18, 2002 Messages 80 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 656 Hi everyone, I need help in designing a circuit for pulse deinterleaving in Verilog HDL for a Xilinx Spartan 2E fpga......if anyone has worked on this before plz reply... Aircraft Maniac
Hi everyone, I need help in designing a circuit for pulse deinterleaving in Verilog HDL for a Xilinx Spartan 2E fpga......if anyone has worked on this before plz reply... Aircraft Maniac