Design with 68hc11 and pseudo-vector

[Debracom]

68hc11 and pseudovector.

We made a test-board with the 68HC, some leds, LCD display, potentiometers, etc...
For the interrupts we use pseudo vectors.

I use the instruction LDAA #$7E. The value gets written to ITOC3. After that, the interruptrouting gets written to ITOC3+1.

This is what I found out :
*A psuedo-vector can be used to place your interrupt routine wherever you want in the ram
*All pseudo-vector are programmed in the internal eeprom with addresses in the ram. *the interrupts vectors cannot be changed, the values in the ram in contrary can.
*Every vector holds a jump function (0x7E) that can take up to three bytes of the ram : 1 byte for the function jump (0x7E) and 2 bytes which point to a address in the ram.

so now my question is : is it possible to call a interrupt with itoc3 or itoc3+1 WITHOUT using a pseudo-vector.

 

[Debracom]

Re: 68hc11 and pseudovector.

nobody that still uses the 68hc11, not even for study purposes that may know this?

 

[Code Warrior]

68hc11 and pseudovector.

Hello,
There is group for MOTOROLA controllers.
https://groups.yahoo.com/group/Motorola_Microcontroller

Regards.

 

[zorro]

Re: 68hc11 and pseudovector.

Hi Debracom

You should put the addres of your interrupt service routine (ISR) at the “true” vector locations, that are in ROM.
Your assembly source could look like this

ORG ITOC3VCT
FDB irq

ORG ITOC5VCT
FDB irq2

where ITOC3VCT and ITOC5VCT are defined as the addresses of interrupt vectors (at the end of memory map in 68hc11, from 0xFFC0 to 0xFFFF).
In this way, the addresses of the ISRs remain fixed. It is good for the application. The pseudovectors are used when you use a monitor program in ROM for debugging, and the adresses of the ISR change each time you download the program in RAM.
Let me know if this is not clear.
Regards

Z

 

[Debracom]

Re: 68hc11 and pseudovector.

Hi Debracom

You should put the addres of your interrupt service routine (ISR) at the “true” vector locations, that are in ROM.
Your assembly source could look like this

ORG ITOC3VCT
FDB irq

ORG ITOC5VCT
FDB irq2

where ITOC3VCT and ITOC5VCT are defined as the addresses of interrupt vectors (at the end of memory map in 68hc11, from 0xFFC0 to 0xFFFF).
In this way, the addresses of the ISRs remain fixed. It is good for the application. The pseudovectors are used when you use a monitor program in ROM for debugging, and the adresses of the ISR change each time you download the program in RAM.
Let me know if this is not clear.
Regards

Z

okay I think I get where this is going. I do not have a monitor program in the ROM. though I don't completely understand how to embed this in the program.

Do I have to set the codes
ORG ITOC3VCT
FDB irq

ORG ITOC5VCT
FDB irq2
before the program, after it. or in my initialisation(which I think). or am I completely wrong here .

for instance, some lines in the initialisation are like this :
ldaa #0x7E ;input code 'jump' to
staa itoc5 ;ram-pseudovector for
staa itoc3 ;interrupt with itoc3&5
ldd #irq ;input address for subroutines.
std itoc3+1
ldd #irq2
std itoc5+1

this all should be changed in the ORG ITOC.... lines ??

Also in the subroutine IRQ there are some lines :
ldd #2000
addd toc3
std toc3
should these be changed too?

thank you for helping, I should never have found it on my own!

 

[zorro]

Re: 68hc11 and pseudovector.

Hello Debracom

Let’s try to clarify.
How do you load your program in the memory? Do you program an EPROM?
The file you uploaded is not the whole program. Could you send me the parts where init, itoc3 and itoc5 are referenced?

Do I have to set the codes
ORG ITOC3VCT
FDB irq

ORG ITOC5VCT
FDB irq2
before the program, after it. or in my initialisation(which I think). or am I completely wrong here .

There is no fixed place in the source code for them.
The directive ORG ITOC3VCT says to the assembler at which absolute address it must point for place the following code, and FDB irq generaes a double byte containing the address of the label irq, defined elsewhere. If your source hay a single module, it is a good practice to put it ad the end with the reset vector (at 0xFFFE) and the other interrupt vectors.

for instance, some lines in the initialisation are like this :
ldaa #0x7E ;input code 'jump' to
staa itoc5 ;ram-pseudovector for
staa itoc3 ;interrupt with itoc3&5
ldd #irq ;input address for subroutines.
std itoc3+1
ldd #irq2
std itoc5+1

this all should be changed in the ORG ITOC.... lines ??

These lines are not needed if you use the interrupt vectors as above. They can be removed.

Also in the subroutine IRQ there are some lines :
ldd #2000
addd toc3
std toc3
should these be changed too?

This sets the Timer Output Compare Register of timer 3, setting the timer for generate a new interrupt 2000 timer ticks after the last one. These lines must be unchanged.

Regards

Z