Design ultralow power, narrow band ADC

[Osawa_Odessa]

Hi,
I want to design an ADC with these specifications:
Fin = 20MHz
BW= 20MHz
ENOB > 4
Power consumption P < 1mW
Could anyone suggest me some ADC for this kind? I have searched a lot in IEEE but there are only two ADC with SAR ADC and time-interleaved ADC.
The ultralow power consumption makes it hard for me to find a architecture. I have little experience about this. Kindly help me.

 

[erikl]

Here's the description of an (up to) 125 Ms/s 6bit 4mW variable sampling rate SAR-ADC, implemented in a 1.8V 0.18µm CMOS process, which should come close to your requirements at 20 Ms/s.

 

[Osawa_Odessa]

Thanks a lot erikl!
That paper look good but there is a problem about power consumption. The requirement that P< 1mW makes it hard to find.

 

[AdvaRes]

Hi Erikl, Hi Osawa_Odessal,

You can expect to ensure this power requirement using lower technology nodes.

 

[erikl]

That paper look good but there is a problem about power consumption. The requirement that P< 1mW makes it hard to find.

Note: The 3.8mW power consumption figure is valid for a sample rate of 125 Ms/s. As this ADC can be operated with variable sample rates, you can expect a power consumption < 1mW at your 20 Ms/s sample rate.

Even less with a lower process size, thanks AdvaRes for this note!