Power = cv^2f* T, where T is the toggle rate = on average the percentage of the nets that are toggling at any time; f is the clock frequency; v is supply voltage; and c is the logic gate capacitance.
With that in mind, it is easy to understand that 1. high frequency nets dissipate high power, by letting it go thru as few hierarchies as possible, it will reduce the toggle rate; 2. gray coding reduces toggle rate.
3 is different issue. Internal tristate bus, if not handled properly, will cause floating nets, which will lead to power leakage.
Hope it helps.