Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design setup for PNR

Status
Not open for further replies.

ramesh28

Member level 3
Member level 3
Joined
May 21, 2013
Messages
57
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Visit site
Activity points
1,670
Hello all,

input files required for PNR flow are as : .lef (layout exchange format), .lib (liberty format), .sdc (synopsis design constraints file), .ptf (process technology file) , .def (design exchange format)

i just want to know that who can genetrate those files and at what steps, these file files gets generated.?

As a pnr engineer can we responsible for generating those files? and as a PNR engineer can we make changes to those files?

please give some useful guidance.

Thank you.
 

.lef, .lib, .ptf should be provided by the IP & technology providers.
.sdc from the synthesis. You forgot the netlist, which should generate from synthesis tool.
I don't know why you need a def file. The PnR job include the floorplan, and this step will generate a DEF.
 
Hi rca,
thanx for reply..

As a PNR engineer can we make changes to .sdc file? or we have to follow constraint file as it is as provided by synthesis guys.

changes in the sense in max capacitance, max transition, etc

i wanted to know about setup margin. means what margin normally be there before placement or after placement? and which constraints decides this setup margin? how can we change it after placement?

thanx.
 
Last edited:

Well, for me the sdc provided by the synthesis guy is correct, or could nbe change via the synthesis engineer.
If you want to apply max_trans/cap rule, you could only reduce the values, and you are not able to relax the value if the max trans/cap are already defined by the .lib file or by the sdc.
The tool use by default the most constrainable values.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top