Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

design phase locked loop using discrete components

Status
Not open for further replies.

nonso

Newbie level 3
Newbie level 3
Joined
Jul 16, 2013
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
25
hi guys i am new here. please i need help. i want to design and construct phase locked loop clock to generate 1000MHz from a local oscillator. i intend to use ce colpitts oscillator to realise the vco. PLL as we all no comes in IC form but i intend to construct it using discrete components which will be used in the lab to teach students fundamentals of PLL. the block diagram consist of Local oscillator, PFD, charge pump, filter, and the VCO. Please anybody with a useful material or link should let me no. thanks. your help will be appreciated. my email nonny4best@yahoo.com
 
Last edited:

If it's just for teaching purposes, it would be much easier if you choose a lower frequency.
 
  • Like
Reactions: nonso

    nonso

    Points: 2
    Helpful Answer Positive Rating
Yes is for teaching purposes. A frequency of 1MHz will be okey
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top