What mystifies me is how long to wait to do things after reset release:
For example would anyone design a circuit that launches a missile immediately after reset release?
Seriously
There is not necessarily anything special about a reset. For example, consider this flip-flop:
Code:
process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
a_reg <= '0';
else
a_reg <= a;
end if;
end if;
end process;
What if we rename the (active-low) reset to
enable
? We might then write it like this:
Code:
process(clk)
begin
if rising_edge(clk) then
a_reg <= a and enable;
end if;
end process;
The two implementations are functionally identical and could be synthesized to identical hardware.
It is not unreasonable to expect the 2nd circuit to "do things" in response to
enable
on the very next rising edge of
clk
. Similarly, it is not unreasonable to expect the 1st circuit to "do things" in response to
rst_n
on the very next rising edge of
clk
. Renaming the signal, or restructuring the HDL code hasn't changed that fact.
If this logic is part of a circuit that controls the launch of a missile, then you would of course need to make absolutely certain that the circuit is not going to behave in an unpredictable manner. That doesn't just apply to a signal that you choose to name a "reset", but to the whole circuit. And it doesn't just apply to circuits that launch missiles; it is very often desirable for a digital circuit to behave predictably in general.