Design of Voltage Reference in Deep Submicron CMOS Process

[JZJIANG]

Hi all,

What are the challenges in designing a voltage reference in deep submicron CMOS process?

To my knowledge, CMOS voltage reference are designed on the basis of vertical/lateral BJTs and MOSFETs in weak inversion, and they are adopted to emulate the behavior of real BJT. But is there any non-ideal factor/characteristic in these two elements in deep submicron CMOS process?

Thank you in advance.

 

[Dominik Przyborowski]

Low supply, in low power processes very high threshold voltages, worst mismatch caused by halo implants, low intrinsic gain of transistors (in order of 10-20), higher influence of short channel effects, some other interesting effects in other than standard SiON planar technology and not accurate modelling...

But of course peoples inviting new solutions for bandgap references. In IEEE Solid State Circuits only in this year more than 10 papers about this topic was published, You have to only check it.

 

[JZJIANG]

Thank you very much for your answer.

BTW, regarding to the inaccurate modeling you mentioned, are you referring to the vertical/lateral BJTs or the MOSFETs in weak inversion, or both? And what causes the inaccurate modeling in deep submicron CMOS process, could you kindly show me any reference papers/books that talking about the inaccurate modelling?

 

[Dominik Przyborowski]

The accurate and continous in each inversion region models are developing, like BSIM6 or PSP but not every PDK provides it so You have to check process documentation and to compare pdk's models with measurements. It is also good to know which physics process is modeled by simulation models or not, i.e. BSIM3 completely doesn't include effects bounded with halo implants, BSIM4 including some of them but not in mismatch parameters.

In solid state electronics and IEEE transactions on electron devices are many papers treating about modelling of mosfets in modern processes.