Design of Timing NCO in digital receiver

[moorthi]

Hi
Pl help me in desinging a timing NCO in the all digital receiver. I'm in the process of designing timing error detector and symbol synchronizer where my smbol rate vary from 5k-500k. I got other building blocks like loopfilter, interpolators and matched filters. But i'm not getting how to go about the timng NCO for the variable symbol rate. Please help me in this

--moorthi

 

[Renjith]

u have ip cores available for the nco for digital receiver.
NCO for a digital receiver will be used for locking the carrier.
u can find plenty of materials related to this on the web itself,
NCO will also be called as DDS "Direct Digit Synthesiser".

Xilinx gives a demo on "QAM Demodulator" using their tool system generator on their web.u can view this demo to get an idea abt the usage of NCO for digital receivers.

 

[moorthi]

In the carrier NCO, error will be calculated and given to NCO for normailised value and the output is given to the cos/sin LUT's. That part is clear to me.

In timing my doubt is how the error is calculated and updaetd and givento the interpolator. All the papers are talking of calculation of error and feed it back to interpolator or other DSP blocks.
Pl carify me in desing of the NCO

The inputs to the system are

1. Symbol rate 1kbps - 32 kbps
2. sampling rate 32Mhz

based on above the NCO regiater is 25-bits.

then how to proceed??????