Okay let's not talk about -6V now...
The Picture in post #25 is for -3.6V. I need similar structure which works as listed before (pulse=0V then output 0V and when it is 1.8V then -3.6V)...
Even when it is 1.8V then -3.3V is acceptable...but at input 0V it should be 0V bottom (output)
Every circuit has it's own complementary circuit. If post #25 is possible then it's complementary is also possible..right..?
You can use the configuration of my post #38. Just replace the Vcp voltage source by a 3.6V source.
Of course it's possible, but I think this won't solve your problem. Just try it!
can you send me the schematic again...?
Why? It's still available!
Yes but for -3.6V why so many stacked transistors....it has to to be 2 stages max..So please could you give me for -3.6V..?
You could easily reduce the number of stages yourself. I'm not your babysitter. :roll:
Show your switch in its current state, including W & L values!
Where do you see latchup?
So this is the output impedance of your charge pump?!I am not using any switch or other circuitry to reduce the resistance value. But the value of Rs =400k now. I need some type to circuitry which will reduce the value to 2-10 ohms.
If you think so: you can't change the substrate resistance of a certain process. If you need a lower substrate resistance, choose a process which uses EPI wafers. Or an SOI process.This is basically the substrate resistance and it should be very very small to avoid latch-up.
So this is the output impedance of your charge pump?!
If you think so: you can't change the substrate resistance of a certain process. If you need a lower substrate resistance, choose a process which uses EPI wafers. Or an SOI process.
So this is the output impedance of your charge pump?!
If you think so: you can't change the substrate resistance of a certain process. If you need a lower substrate resistance, choose a process which uses EPI wafers. Or an SOI process.
So this is the output impedance of your charge pump?!
If you think so: you can't change the substrate resistance of a certain process. If you need a lower substrate resistance, choose a process which uses EPI wafers. Or an SOI process.
So this is the output impedance of your charge pump?!
If you think so: you can't change the substrate resistance of a certain process. If you need a lower substrate resistance, choose a process which uses EPI wafers. Or an SOI process.
I would like to update you that Rs=400K is the output resistance of the charge pump circuit and Vout=-6V is given to the P-well in the CMOS 180nm technology.
To avoid confusion let's call it as Rout= 400K....
I want to reduce this resistance value to few tens of ohms..Could you suggest me anything..??
Where is your P-well? In an N-well of a p-substrate or directly in an n-substrate? Show your process details (doping of well(s) and EPI layer) if you want help!
Rout=400kΩ seems quite normal at a load current of 1µA (you loose just 400mV). I don't think you can do better, even with a different charge pump.
No, I can't suggest a better solution, sorry.
Where is your P-well? In an N-well of a p-substrate or directly in an n-substrate? Show your process details (doping of well(s) and EPI layer) if you want help!
Rout=400kΩ seems quite normal at a load current of 1µA (you loose just 400mV). I don't think you can do better, even with a different charge pump.
No, I can't suggest a better solution, sorry.
Could you tell me how did you calculate 400mV loss...??
Where is your P-well? In an N-well of a p-substrate or directly in an n-substrate? Show your process details (doping of well(s) and EPI layer) if you want help!
Rout=400kΩ seems quite normal at a load current of 1µA (you loose just 400mV). I don't think you can do better, even with a different charge pump.
No, I can't suggest a better solution, sorry.
Thanks a lot...I would like to update you that when the supply VDD=0V then the output resistance of my charge pump is ~400K. But when the supply is 1.8V then the output impedance is ~8K at 1uA of load current...The worrying problem is during the start-up condition...I think this won'y work in the real time due to latch-up problem...What do you say on that..??
- - - Updated - - -
The idea is to have very low resistance when the supply is 0V....
Where is your P-well? In an N-well of a p-substrate or directly in an n-substrate? Show your process details (doping of well(s) and EPI layer) if you want help!
Rout=400kΩ seems quite normal at a load current of 1µA (you loose just 400mV). I don't think you can do better, even with a different charge pump.
No, I can't suggest a better solution, sorry.
Have you ever heard of Ohm's Law? Then use it!
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