... when the supply is ON, then it should give me -6V.
For stacked voltage division transistors in separate wells it's of course possible to limit their voltage difference to 1.8V . But in any case - because of a common substrate of a bulk CMOS process - you unavoidably have somewhere the total of 1.8V + |-6V| = 7.8V between two different nodes. A 1.8V process won't tolerate this.
For stacked voltage division transistors in separate wells it's of course possible to limit their voltage difference to 1.8V . But in any case - because of a common substrate of a bulk CMOS process - you unavoidably have somewhere the total of 1.8V + |-6V| = 7.8V between two different nodes. A 1.8V process won't tolerate this.
I am saying again the 1st schematic which I have used in my circuit has all the operating point less than 1.8...I am just wondering if that can work then reverse to it can also happen..right..??
...
Please see this schematic.. I have used this..View attachment 144420
...
Remember I am doing 6 stage charge pump.. so instead of -3.6V i have -6V (regulated) so I need 6 stages...
...
This schematic works totally fine...I want something similar when in opposite way..
Sure, it works fine in schematic - but not in a 1.8V CMOS bulk process layout. It could work in a 1.8V CMOS SOI process with totally isolated substrates. Unfortunately you never revealed if you intend to use a bulk or a (essentially more expensive) SOI process.
Report your process - otherwise it doesn't make sense to go on.
Okay..But I am saying again the 1st schematic which I have used in my circuit has all the operating point less than 1.8.
Please see this schematic.. I have used this..View attachment 144420
I want similar type of functioning but in opposite way..
When input is 0...I should get 0 at the output of the charge pump..and when I give 1.8V then output should be -3.6V....
Remember I am doing 6 stage charge pump.. so instead of -3.6V i have -6V (regulated) so I need 6 stages...
This schematic works totally fine...I want something similar when in opposite way..
Could you share a schematic with works fine in the schematic...?? the operating point should be less than 1.8\v
That's not correct: neither does its output switch between 0 and -3.6V (it switches between -1.8 and -3.6V), nor are the voltage differences at a single transistor less than 1.8V, s. this simulation output:
View attachment 144457
When the input voltage is HI (+1.8V), P2's Vgs=-2*1.8V , N2's Vgs=3*1.8V .
- - - Updated - - -
No, this wouldn't work with an inverter, sorry.
Please add 100M resistance after -3.6V of voltage source as shown in the modified schematic.. Width NMOS is 100um and PMOS is 20 um.
Ok, with this change (100MΩ resistor between -3.6V and output) the circuit operates as you described it in the beginning - I didn't notice this resistor, and you didn't mention it before, nor did you ever tell where's your output.
View attachment 144511
There was a lot of misunderstanding, because you didn't give enough info in due time!
Now we need to do some modification in this circuit or try for a similar type switch...
So Please could you guide me with a circuit similar to this but the condition is when input is 0 then i should get 0 at the output and when I give 1.8V then I should get -3.6V...
Ok, with this change (100MΩ resistor between -3.6V and output) the circuit operates as you described it in the beginning - I didn't notice this resistor, and you didn't mention it before, nor did you ever tell where's your output.
View attachment 144511
There was a lot of misunderstanding, because you didn't give enough info in due time!
Me too, sorry. Good luck!I am still unable to proceed...
In my eyes it doesn't make sense to use a 1.8V process for a circuit which operates on 8V supply (6+1.8V). If ever possible for your task, it would need a rather complex circuit with 5 or 6 stacked transistors in every branch, compared to an essentially simple circuit using the right process, e.g. a 0.5 or a 0.35µm HV SOI process. Due to the 5 or 6 times more devices necessary +routing it could even take more silicon area than a 0.18µm 1.8V process.
But perhaps this is just an academic job? I already told you this doesn't work with a simple inverter circuit. May be you - or someone else - can find a better method.
Me too, sorry. Good luck!
In my eyes it doesn't make sense to use a 1.8V process for a circuit which operates on 8V supply (6+1.8V). If ever possible for your task, it would need a rather complex circuit with 5 or 6 stacked transistors in every branch, compared to an essentially simple circuit using the right process, e.g. a 0.5 or a 0.35µm HV SOI process. Due to the 5 or 6 times more devices necessary +routing it could even take more silicon area than a 0.18µm 1.8V process.
But perhaps this is just an academic job? I already told you this doesn't work with a simple inverter circuit. May be you - or someone else - can find a better method.
Me too, sorry. Good luck!
Hi,
I know little about this. Wouldn't that require for example an internal inverting charge pump to achieve the -6V out from +1.8V in? Not the same, but - as far as I recollect - the LMV791 has an internal charge pump. Don't know if that direction of design would be of benefit.
Like this?
You need low threshold MOSFETs.
Please try to make such stacked circuit...I am seriously blank..I really don't have good scheme..
Please guide me with some solution...
Here's a trial circuit for a stacked design: a stacked inverter used in a negative current feedback circuit:
View attachment 144823 View attachment 144824
The 2 FETs close to the output still need to sustain about 3V.
By extending the stacked branches to even more transistors you still could press down the necessary sustain voltage of the 2 last FETs adjacent to the output, however on the other hand you'd then loose even more output voltage.
A 1.8µm process usually offers 3.3 or even 5V I/O transistors.
Remember: you still need an SOI process with total substrate isolation for the -6V charge pump voltage and for the stacked transistors.
Yes 0.18µm process provides 3.3 and 5V in my case... But I can't use them because of extra masking and process..Okay let's not talk about -6V now...
The Picture in post #25 is for -3.6V. I need similar structure which works as listed before (pulse=0V then output 0V and when it is 1.8V then -3.6V)...
Basically complementary of post #25...
Yes 0.18µm process provides 3.3 and 5V in my case... But I can't use them because of extra masking and process..Okay let's not talk about -6V now...
The Picture in post #25 is for -3.6V. I need similar structure which works as listed before (pulse=0V then output 0V and when it is 1.8V then -3.6V)...
Basically complementary of post #25...
- - - Updated - - -
Even when it is 1.8V then -3.3V is acceptable...but at input 0V it should be 0V bottom (output)
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