This schematic works as input 1.8V then output is 0. When input is 0V out is -3.6V.
I need in opposite way.
A trivial solution would be to invert your Pulse signal.
Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.I need to design a switch which works such that when we give 1.8 as the control signal which is my input as shown in the picture it should give me -3.6V. and when I give 0 at the input I should get 0 at the output.
Basically I need a configuration as transistors are stacked as shown below in the picture.
Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.
Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.
VDS of both the transistors are more that -3.5V which is not okay. CMOS 180nm technology. VDD is 1.8V.
please guide me with the solution.
Does your process offer 5V (I/O) transistors?
BTW: In a bulk CMOS technology (p-substrate) you can't use negative voltages. The p-substrate must be your most negative potential.
If your process offers only transistors which can stand max. 1.8V , it should be clear that you chose the wrong process for your task.
And remember: for bulk p-substrate CMOS processes, the p-substrate must be the most negative potential.
This does not work:
View attachment 144240
Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.
Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.
I need same type of switch but in opposite way. Input 0 then output 0. When input 1.8V then output -3.6V.
By the way the first comprehensible schematic in this thread, showing input, output, power supply...you could try something like that
By the way the first comprehensible schematic in this thread, showing input, output, power supply...
If you think you can realize this with your process - you didn't tell if you'd use a p-substrate, an n-substrate or an SOI technology - you could try something like that:
View attachment 144255 Note the N3:N4 aspect ratio!
If you think you can realize this with your process - you didn't tell if you'd use a p-substrate, an n-substrate or an SOI technology - you could try something like that:
View attachment 144255 Note the N3:N4 aspect ratio!
could you please give me a schematic as if input 0 then output 0, but when input 1.8V output should be -6V ... Please guide me with the solution
In this case you can renounce on N3, but you need a huge aspect ratio for P1:N4 .
View attachment 144397
For P1 & N2 you need transistors which can stand at least 8V (and for the others at least 6V , of course). And an SOI process, I'd think.
Thanks a lot for this...I agree..But the problem is i am using CMOS 180nm process....1.8V is the max...
please help me with some other circuitry...I am also trying...but ...
Thanks a lot for this...I agree..But the problem is i am using CMOS 180nm process....1.8V is the max...
please help me with some other circuitry...I am also trying...but ...
The problem is ... with a 1.8V process you cannot realize an 8V circuit on the same chip. The same applies for your -6V charge pump. You either need a process which offers min. 8V transistors (perhaps an SOI process with isolated substrates), or you have to realize the -6V charge pump and its switch externally.
The problem is ... with a 1.8V process you cannot realize an 8V circuit on the same chip. The same applies for your -6V charge pump. You either need a process which offers min. 8V transistors (perhaps an SOI process with isolated substrates), or you have to realize the -6V charge pump and its switch externally.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?