design of flash adc(refrence generation)

[niket_jmd]

i m working on flash adc..........i m using fully differentail topology. i m using sample and hold circuit. my input range is .6 tp - .6(1.2v p to p) nd 3.3v supply. At the o/p of sample nd hold this signal is biased at dc level 1.6v. this o/p goes to diff amplifier where it will be compared with refrence voltage. My question is how to bias the refrence voltage at that particular level. Is there some other tefchnique??

 

[A.Anand Srinivasan]

reference voltage is generated by using bandgap reference which are stable voltage sources with respect to variation in temperature... so we implement a resistive ladder and take the required voltage values from that....

 

[niket_jmd]

i was unable to explain my point. I m using fully diffrential topology.
my i/p range is -.6 to +.6 . after passing through s/h the samw signal will be biased at common mode voltage (1.6v).so vout+ and vout- frm s/h will have variation on 1.6v bias. This will be given to difference amplifier where it will be compared with vref+ and vref-.now some how for correct comparision i hav to bias refrence at 1.6v also otherwise comparision is not possible............so actually wht is the way??

 

[A.Anand Srinivasan]

the way is to generate a voltage source for 1.6V which is stable against temperature variations... this voltage source is called bandgap reference and search for topics on this and you will understand what i'm saying....