If you don't have any unusual requirements like cold-sparing
(i.e. output does not leak back when VDD=0) then the usual
CMOS digital ESD schemes could be applied. If you need
"power off high impedance" on the outputs then probably
need to use a GGNMOS clamp per output (possibly with a
back diode).
Verifying ESD performance can be a problem because the
device operates in two modes which interest modeling
engineers not at all; "off" and "snapback". I've run into
nothing but apathy there and always had to fit my own
models (I tend to just overlay a properly parameterized
diode model, kill the forward and fit the reverse params).
But you need TLP data to get at the post-snapback
resistance.