Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design of Equalizer in Verilog on FPGA

Status
Not open for further replies.

yvahini

Newbie level 3
Joined
Apr 1, 2009
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,301
equalizer verilog

I was given a project

Implement a three band equalizer in Verilog,on an Xilinx spartan III FPGA....

Can you please give any code or related block diagram if possible......
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top