Mar 29, 2012 #1 B bvishwanath Junior Member level 1 Joined Mar 17, 2011 Messages 19 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,391 when using sequential code to design combinational logic in vhdl if completle truth table is not defined ,the synthesis tool implement______________which is not requried 1.clock buffer 2.buffer 3.flip flop 4.latch
when using sequential code to design combinational logic in vhdl if completle truth table is not defined ,the synthesis tool implement______________which is not requried 1.clock buffer 2.buffer 3.flip flop 4.latch
Mar 29, 2012 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 is the answer 1?