ssubha
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I want to design 4-way set associative cache of eight sets. i use the following verilog code to view this as array of 32 entries.
reg[0..7] sa[0..31];
can i selectively put off the array elements using power gating thus disabling the cache ways? is there any better method to achieve this?
reg[0..7] sa[0..31];
can i selectively put off the array elements using power gating thus disabling the cache ways? is there any better method to achieve this?