Because I need to make all transistor to operate in saturation region. But at last i still cant make it by changing its width and length. So, what i can do to solve this problem. Thanks.
Get rid of some stack height, which eats headroom.
Not all transistors get to be in saturation, all the time.
Regardless what you may think you want or "need".
Sometimes you just have to deal with that.
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Thanks for the reply.
Here is my parameter for the design.
Input voltage = 1.65 V to 2 V
Output voltage = 1.6 V
Load current range = 9uA to 1.1mA
Is it possible to make that?
Possible? Probably.
You need to first get to a pass FET which will throw
2mA @ VTP-1V (or so) and 50mV Vds at slow*cold
(worst case VT) and slow*hot (worst case IDsat@Vgs)
and leak less than 1uA @ fast*hot, Vds=0.5V (make that
Vds=2V, if this LDO is supposed to also remove power
(e.g. for standby current spec).
Your pass FET should for sure come from the ESD library
(if FETs are there) or have ESD rules checked in the
symbol & PCell (when you get to layout). That's a pin-pin
pinata device application.