Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

design methos for D flip flop using TSPC

Status
Not open for further replies.
D

dili Neo

Junior Member level 2
Junior Member level 2
Joined
Aug 21, 2012
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,405
Hi all,

I am trying to design a D flip flop using TSPC . I am using this architecture: https://upload.wikimedia.org/wikipe...e_edge-triggered_flip-flop_with_reset.svg.png

I want to know how to size the NMOS and PMOS. I am working in TSMC65nm. I am looking for a methodology on transistor sizing in TSPC. I am using a pulse of 180ns pulse width and time period 300ns as D input while clock is of time period 50ns.

Kindly help me with this.Thanks in advance

Cheers
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top