Well, a frequency ramp sounds a lot like a phase parabola to me. A type 2 system will track such a frequency ramp, although with a static error in the steady state (error gets smaller with more open loop gain). A type 3 system, as a minimum, will track such a frequency ramp with zero error in the steady state, (although there might be some ringing at start up of the ramp).
By type 3, I mean a PLL with two integrators (poles at zero frequency) in the loop filter, and the 3rd integrator in the oscillator's Kvco/s. To get started, I would just design it using standard Bode diagram conditions (phase and gain margin constraints). If you want to get fancier, a root locus analysis or Nichols plot will add insight. I would definitely add the divider's time delay into the analysis, as that might give you a steady state error and some interesting start up effects--i.e. keep the divisor ratio small!
But maybe you are using the wrong thing to track this? A frequency ramp might better be tracked with a frequency locked loop, not a phase locked loop?
Rich