design loop filters of type 3 and type 4 and order 3 and

[aswinkumarv]

type-3 pll

I want to design loop filters of type 3 and type 4 and order 3 and 4.can i cascade two type 2 to get type 3

 

[saro_k_82]

Re: type 4 pll

Are you asking about the order of the LPF or the type?.,
A type 2 system has two poles at the origin whereas a TF with order two has two poles anywhere.
Can you also make it clear as to what necessitates a 4th order(or type) PLL

 

[LvW]

Re: type 4 pll

I want to design loop filters of type 3 and type 4 and order 3 and 4.can i cascade two type 2 to get type 3

In order to avoid misunderstandings may I propose something to you:

Please, express yourself as clear as possible (in your own interest) and don´t use short terms (like filter of type xyz) which are not commonly agreed upon.
Instead, use the terms "active" and "passive" with/without a zero.
Otherwise, not everybody who could answer your question will or can do that.
Regards

 

[aswinkumarv]

Re: type 4 pll

I want to generate linear frequency ramp

 

[saro_k_82]

Can you describe your problem in detail. I don't think anyone would have understood your exact requirement.

 

[FvM]

We are not in a guessing game. If you're targetting e.g. to a PLL design, you may want to tell it clearly. If you are refering to any available literature, you should mention it.

 

[aswinkumarv]

I want to track frequency ramp which is given to the reference input of the PLL.

Now if i use some N counter value I could multiply the sweep which i have fed in the reference port

also please suggest me literature to know more about sigma delta modualtor based PLL.

 

[biff44]

Well, a frequency ramp sounds a lot like a phase parabola to me. A type 2 system will track such a frequency ramp, although with a static error in the steady state (error gets smaller with more open loop gain). A type 3 system, as a minimum, will track such a frequency ramp with zero error in the steady state, (although there might be some ringing at start up of the ramp).

By type 3, I mean a PLL with two integrators (poles at zero frequency) in the loop filter, and the 3rd integrator in the oscillator's Kvco/s. To get started, I would just design it using standard Bode diagram conditions (phase and gain margin constraints). If you want to get fancier, a root locus analysis or Nichols plot will add insight. I would definitely add the divider's time delay into the analysis, as that might give you a steady state error and some interesting start up effects--i.e. keep the divisor ratio small!

But maybe you are using the wrong thing to track this? A frequency ramp might better be tracked with a frequency locked loop, not a phase locked loop?

Rich