Great!
That means that they gave us the right one!
But i don't find in its userguide that they mentioned anything about standard-cells for PADs design and other packaging issues.. Is it a big problem?? i.e. how else could we design (layout) for the complete chip?
Yes if u are designing a complete chip and u will need pads and standard cells for digital, it will be a big problem if u don't already have them in the design kit.
Yes if u are designing a complete chip and u will need pads and standard cells for digital, it will be a big problem if u don't already have them in the design kit.
Let me ask a little question here, what do you mean with PADs?
Is there specific pCell for pads in layout? and it's a PDK issue?
How can i check if i have them or not..
Moreover, For a chip that have mixed analog and digital blocks, how can they be put together in layout although analog blocks layout is done almost from scratch whereas you just wanna place and rout digital blocks..!
Concerning the pads, yes it depends on ur design kit u may and maynot have pads,to check if u have pads or not u can go through the PDK documentation or simply search in the design kit libraries.
I think if u don't have them u can ask for , but ofcourse that's not free $$$.
Concerning the mixed-signal , I don't know what's the exact flow in case u have huge digital blocks that needs complicated P&R.
What's Voila??
Then, the problem is in making use of digital PDK to synthesis and P&R then generate layout, and combine this with analog layout on the same chip!
u do the digital on its own synthesis, then P&R to fill a specific space on the Chip then copy the generated layout then paste it in the empty space, connect the interfaces then Voila again
BTW i think there are many IPs done this way , like in interfaces (like SPI) where it is an already made digital part with a specific area u buy it then paste it in ur layout and that is it "w2llahoo 2a3llam"