Sorry, I'm newbie. I have 3 problems that can not be solve more than 1 week. I need solve as soon as possible.
Firstly, please help me draw schematic in Cadence about D Flip Flop using NMOS and PMOS or something like these.
Secondly, please help me draw schematic 8-bit register with that D-FF.
Thirdly, please help me how I can connect PLL (Phased-Locked-Loop) with a 8-bit register which contains the input value to choose frequency in PLL ( Ex: when I choose 00000001, frequency is 50Hz; 00000010, frequency is 100Hz...)
So, do you really have to draw that entire circuit eight times and hook them all together? Instead it should be sufficient to draw the usual icon with 4 or 5 terminals.
In your first post you didn't say anything about "analog".
--> a flipflop usually is digital
--> a 8 bit DFF is digital
--> a PLL is digital (only the filter is a passive -analog- one and the VCO)
Please tell exactely where you see the problems. In my eyes a FF, a DFF and a PLL are very common circuits with more than enough documentation around.
Added:
Your 8 bit DFF to choose output frequency need to act as a "divider" (counter, compare, reset) and needs to be installed in the feedback path of the PLL, so it acts as a "multiplier".
But this is shown and described in any PLL documentation.
Btw: you are talking about relatively low output frequencies with high dynamics (1:255), therefore the use of an NCO instead of a PLL may be more suited.
So, do you really have to draw that entire circuit eight times and hook them all together? Instead it should be sufficient to draw the usual icon with 4 or 5 terminals.
In your first post you didn't say anything about "analog".
--> a flipflop usually is digital
--> a 8 bit DFF is digital
--> a PLL is digital (only the filter is a passive -analog- one and the VCO)
Please tell exactely where you see the problems. In my eyes a FF, a DFF and a PLL are very common circuits with more than enough documentation around.
Added:
Your 8 bit DFF to choose output frequency need to act as a "divider" (counter, compare, reset) and needs to be installed in the feedback path of the PLL, so it acts as a "multiplier".
But this is shown and described in any PLL documentation.
Btw: you are talking about relatively low output frequencies with high dynamics (1:255), therefore the use of an NCO instead of a PLL may be more suited.
This problem is related to Analog, but I look for some information, which only show Digital design.
Now, I am using PLL, this is mentor's requirement, it can not be changed.
Please show me block diagram by your drawing.
Please remember, when a person want to choose 50Hz, they will press 00000001, and etc ...