Aggieland
Newbie level 5
In His Name
Hello everybody
I am new in ASIC Design and I have a problem.
I am trying to do pipeline retiming for my verilog code using design compiler.
The problem is I need to know the power usage of each stage of pipeline separately.
Can anybody help me?
Please, Please Help me.
Regards;:?:
Hello everybody
I am new in ASIC Design and I have a problem.
I am trying to do pipeline retiming for my verilog code using design compiler.
The problem is I need to know the power usage of each stage of pipeline separately.
Can anybody help me?
Please, Please Help me.
Regards;:?: