Design a low phase noise frequency systhesizers

[frever]

I want to desgin a singal source that outputs 5GHz with 116dBc/Hz@10kHz. But it is difficult to reach the target by integrated PLL. Could someone give me some advices to get the target?
Thank you!

 

[sunnySan]

You could also use a pin diode and make it to oscillate at the chosen frequency by making it unstable

 

[biff44]

You are not specifying phase noise in the proper units--not sure what you mean. You need dBc/Hz

For a fixed 5 Ghz output, get a varactor tuned dielectric resonator oscillator, preferably made with a silicon bipolar transistor, and phase lock it in a very narrow loop bandwidth. Use the smallest divisor ratio (or highest comparison frequency) possible with your PLL chip (shoot for 50 MHz, for instance). Keep the loop bandwidth at 500 Hz or so, and you will have a shot if the DRO is low enough phase noise.

And use a good clock, and low phase noise chip.

In short, find a DRO oscillator whose free running noise meets your specification, and phase lock it in a narrow bandwidth to keep from screwing up the noise.

If your spec is too tight, or you need a tunable synthesizer, things are much more complicated.

 

[frever]

Thank you for your reply!
If I use the integreted PLL, the noise from it is always more than -100dBc/Hz when it works at 5GHz. Could you introduce some special PLL with low noise?

 

[hanm]

Your phase noise seems too rigorous to reach!

 

[biff44]

Sorry, I gave you poor suggestion. Free running DRO noise is 10 dB short of your spec. You will need to do something more involved. Are we talking about a single frequency?