You are not specifying phase noise in the proper units--not sure what you mean. You need dBc/Hz
For a fixed 5 Ghz output, get a varactor tuned dielectric resonator oscillator, preferably made with a silicon bipolar transistor, and phase lock it in a very narrow loop bandwidth. Use the smallest divisor ratio (or highest comparison frequency) possible with your PLL chip (shoot for 50 MHz, for instance). Keep the loop bandwidth at 500 Hz or so, and you will have a shot if the DRO is low enough phase noise.
And use a good clock, and low phase noise chip.
In short, find a DRO oscillator whose free running noise meets your specification, and phase lock it in a narrow bandwidth to keep from screwing up the noise.
If your spec is too tight, or you need a tunable synthesizer, things are much more complicated.