Hi Radix,
Thank you for your quick reply.
First of all, the clock used for the internal virtex is derived from the clock used to drive the line.
So for the demux part, I will need a FIFO to capture the data coming in at 625MHz and write the 256bit vector into the RAM at 39MHz. Is the FIFO about to run at 625Mhz?
For the mux part, how am I able to grab the 256bit vector from the RAM and output 16bit vectors at 625Mhz? Please advise
One last question, say the top level entity consists of the demux, RAM and mux, do i need to synthesize the top entity to 625Mhz. Is it possible for virtex 4 to run at such speeds?
Thank you very much..