brainiac_rus
Newbie level 5
- Joined
- May 28, 2014
- Messages
- 10
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1
- Activity points
- 103
Hello!
I have a board with fpga spartan 6 and serializer sn65lv1023a deserializer sn65lv1224b. There is a channel between serializer and deserializer which can be work on speed from 120 to 720 MHz. In my case it works on 120 MHz.
My problem is that there many errors in receiving packets, when i increase speed of channel. I use 8b/10b encoding for decrease errors and use crc8 for deleting bad packets. My first question is how to latch data from deserializer - there is recovered clock from deserializer and when there is rise of clock - data is valid. I tried to increase clock of receiving data module in fpga to 5x of frequency of deserializer and catch transition from zero to one of clock line deserializer. But when i increase a speed of transmission between ser/des there will be timing errors on my fpga. I think about other ways of solving this problem - using latches and catch data when recovered clock of deser is ''1'' - but i think this is wrong way. Second way is to use clock of deser to clock some flip-flops and then use syncronization circuit with 2 flip-flops clocked with inner clock in fpga, because there can be setup/hold problems. But on my pcb recovered clock connects with simple pin of fpga, not pin for input clock. And i think that second way is bad too. Is there some mistakes in my thoughts and are there another ways to latch data?
I have a board with fpga spartan 6 and serializer sn65lv1023a deserializer sn65lv1224b. There is a channel between serializer and deserializer which can be work on speed from 120 to 720 MHz. In my case it works on 120 MHz.
My problem is that there many errors in receiving packets, when i increase speed of channel. I use 8b/10b encoding for decrease errors and use crc8 for deleting bad packets. My first question is how to latch data from deserializer - there is recovered clock from deserializer and when there is rise of clock - data is valid. I tried to increase clock of receiving data module in fpga to 5x of frequency of deserializer and catch transition from zero to one of clock line deserializer. But when i increase a speed of transmission between ser/des there will be timing errors on my fpga. I think about other ways of solving this problem - using latches and catch data when recovered clock of deser is ''1'' - but i think this is wrong way. Second way is to use clock of deser to clock some flip-flops and then use syncronization circuit with 2 flip-flops clocked with inner clock in fpga, because there can be setup/hold problems. But on my pcb recovered clock connects with simple pin of fpga, not pin for input clock. And i think that second way is bad too. Is there some mistakes in my thoughts and are there another ways to latch data?
