Describe in Verilog a RALU circuit that has 8 functions for operands on 4 bits.

[Mihai Patrascioiu]

Hello i've got a mini project to make and i don't have a lot of knowledge in Verilog programming. I want some help, please!

The task is : Describe in Verilog a RALU circuit that has 8 functions for operands on 4 bits.

Here is some of what i've found but it's not operational

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Code Verilog - [expand]
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module ralu(
        input [3:0] in,
        input [3:0] func,
        input clock,
        input load,
        output [3:0] out
   
);
    
 
reg [3:0] op1;
reg[3:0] op2;
always@(posedge clock)
 
if(load) op2<=in;
else op1<=in;
 
 
endmodule
 
module alu(
        input [3:0] op1,
        input [3:0] op2,
        input [3:0] func,
        output reg [3:0] out
    );
 
always@(*)
case(func)
3'b000: out=op1|op2;
3'b001: out=op1&op2;
3'b010: out=!op1&!op2;
3'b011: out=!op1|!op2;
3'b100: out=op1^op2;
3'b101: out=!op1^!op2;
3'b110: out=op1+op2;
3'b111: out=op1-op2;
endcase
 
endmodule

---

 

[ads-ee]

You have to instantiate the alu module inside the ralu module if you want to have the op1, op2, func, and out to connect to anything in ralu.

Right now you have two separate modules with no connections between them.

You should fix the width of func, it's defined as 4-bit but should only be 3-bits. Add a default to the case and set it to out = 4'bxxxx;.

Anticipating the next question, this is how you instantiate.

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Code Verilog - [expand]
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module test (
  input a
  input b
  output c
);
  sub_mod  instance_name (
    .a   (a),
    .b   (b),
    .c   (c)
  );
endmodule
 
module sub_mod (
  input a,
  input b,
  output c
);
  assign c = {a, b, a^b, a & b};
endmodule

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Regards