------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -1.055 | -0.797 | -1.055 | -0.721 | 4.389 | N/A |
| TNS (ns): | -1521.3 |-232.758| -1397.5 | -30.677 | 0.000 | N/A |
| Violating Paths:| 3215 | 1251 | 2332 | 131 | 0 | N/A |
| All Paths: | 4559 | 3152 | 2473 | 288 | 16 | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.761 | -0.246 | 1.088 | -0.761 | 0.847 | N/A |
| TNS (ns): | -85.824 | -13.244 | 0.000 | -72.580| 0.000 | N/A |
| Violating Paths:| 474 | 210 | 0 | 264 | 0 | N/A |
| All Paths: | 4558 | 3151 | 2472 | 288 | 16 | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
How much margin you are keeping for hold
I dont have any margin for now, .
velocity 30> getOptMode
-addInst true # bool, default=true
-addInstancePrefix {} # string, default=""
-addNetPrefix {} # string, default=""
-addPortAsNeeded true # bool, default=true
-allEndPoints false # bool, default=false
-allowOnlyCellSwapping false # bool, default=false
-bufferAssignNets false # bool, default=false
-clkGateAware false # bool, default=false
-congOpt false # bool, default=false
-considerNonActivePathGroup false # bool, default=false
-criticalRange 0.2 # float, default=0.2, min=0.000000, max=1.000000
-critPathCellYield false # bool, default=false
-deleteInst true # bool, default=true
-downsizeInst true # bool, default=true
-drcMargin 0 # float, default=0, user setting
-dynamicPowerEffort none # enums={none low med high}, default=none
-effort high # enums={low high}, default=high, user setting
-fixCap true # bool, default=true, user setting, private
-fixDrc true # bool, default=true
-fixFanoutLoad true # bool, default=false, user setting
-fixGlitch true # bool, default=true
-fixHoldAllowOverlap auto # enums={auto false true}, default=auto
-fixHoldAllowSetupTnsDegrade true # bool, default=true
-fixHoldOnExcludedClockNets false # bool, default=false
-fixTran true # bool, default=true, user setting, private
-holdFixingCells {} # string, default=""
-holdFixingEffort low # enums={low high}, default=low
-holdSdfFile {} # string, default=""
-holdTargetSlack 0 # float, default=0
-honorFence false # bool, default=false
-ignorePathGroupsForHold {} # string, default=""
-keepPort {} # string, default=""
-leakagePowerEffort none # enums={none low high}, default=none
-maxDensity 0.95 # float, default=0.95
-maxLength 2147483647 # uint, default=2147483647
-moveInst true # bool, default=true
-optimizeConstantNet true # bool, default=true
-optimizeFF true # bool, default=true
-optimizeNetsAcrossDiffVoltPDs true # bool, default=true
-postCtsClkGateCloning false # bool, default=false
-postRouteAllowOverlap true # bool, default=true
-preserveAssertions true # bool, default=true
-preserveModuleFunction false # bool, default=false
-reclaimArea default # enums={true false default}, default=default
-resizeShifterAndIsoInsts false # bool, default=false
-restruct true # bool, default=true
-route noPreserve # enums={post incrNano incrTrial incr noIncr preserve noPreserve}, default=incrTrial, user setting, private
-setupSdfFile {} # string, default=""
-setupTargetSlack 0 # float, default=0, user setting
-simplifyNetlist true # bool, default=true
-sizeOnlyFile {} # string, default=""
-swapPin true # bool, default=true
-unfixClkInstForOpt true # bool, default=true
-useConcatDefaultsPrefix true # bool, default=true
-usefulSkew false # bool, default=false
-verbose false # bool, default=false
-virtualPartition false # bool, default=false
-yieldEffort none # enums={none low high}, default=none
********** Clock clk_i Pre-Route Timing Analysis **********
Nr. of Subtrees : 1
Nr. of Sinks : 2939
Nr. of Buffer : 69
Nr. of Level (including gates) : 4
Root Rise Input Tran : 120(ps)
Root Fall Input Tran : 120(ps)
Max trig. edge delay at sink(R): top0/.../.../mem_reg_8__10_/CK 392.7(ps)
Min trig. edge delay at sink(R): top0/.../.../.../CK 362(ps)
(Actual) (Required)
Rise Phase Delay : 362~392.7(ps) 0~10(ps)
Fall Phase Delay : 433.5~523.7(ps) 0~10(ps)
Trig. Edge Skew : 30.7(ps) 120(ps)
Rise Skew : 30.7(ps)
Fall Skew : 90.2(ps)
Max. Rise Buffer Tran. : 219.5(ps) 300(ps)
Max. Fall Buffer Tran. : 129.6(ps) 300(ps)
Max. Rise Sink Tran. : 231.5(ps) 300(ps)
Max. Fall Sink Tran. : 261.6(ps) 300(ps)
Min. Rise Buffer Tran. : 73.8(ps) 0(ps)
Min. Fall Buffer Tran. : 60.3(ps) 0(ps)
Min. Rise Sink Tran. : 137.2(ps) 0(ps)
Min. Fall Sink Tran. : 98.7(ps) 0(ps)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.826 | -0.256 | 1.061 | -0.826 | 0.900 | N/A |
| TNS (ns): |-456.987 |-283.399 | 0.000 |-173.588 | 0.000 | N/A |
| Violating Paths:| 2172 | 1882 | 0 | 290 | 0 | N/A |
| All Paths: | 4759 | 3263 | 2478 | 290 | 16 | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
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