delay units in pipelined ADC

[juba]

I'm making a pipeline ADC and I need to have a delay unit that delays the signal (in my case for 20ns).
I have a clock that its pulse width is 20ns (pulse width not pulse period)
how can I get my delay?

 

[erikl]

If the ADC is clocked with the positive edge of this clock pulse, clock (latch) the signal to be delayed with the negative going clock pulse edge - or the other way round. If necessary, invert the clock pulse to catch the correctly delayed clock edge.