groover
Junior Member level 1
Hello, using Verilog and I am creating a 'memory', e.g.:
This memory is read/write accessible via a bus, and some of the bits will be read only and some will be write only.
I am trying to construct a "core-wide" set of definitions to use throughout my core so I can easily change the memory descriptions in one place. For example I have a file RegisterDefinitions.v containing:
then in my registers module:
How can I define the read/write masks in a generic way, so that I can easily add a new mask if I add a new register? For example in C I would do:
then when accessing register n I would OR with it ReadMasks[n].
I know I can do:
Thanks!
- - - Updated - - -
OK, after some thinking I came up with this:
in the header file:
Comments welcome.
Code:
reg [7:0] registers [0:4];This memory is read/write accessible via a bus, and some of the bits will be read only and some will be write only.
I am trying to construct a "core-wide" set of definitions to use throughout my core so I can easily change the memory descriptions in one place. For example I have a file RegisterDefinitions.v containing:
Code:
`define REG_NUMBEROFREGISTERS 4then in my registers module:
Code:
reg [7:0] registers [0:`REG_NUMBEROFREGISTERS];How can I define the read/write masks in a generic way, so that I can easily add a new mask if I add a new register? For example in C I would do:
Code:
#define READ_MASKS { 0x5C, 0xFF, 0xAA };
unsigned char ReadMasks[4] = READ_MASKS;then when accessing register n I would OR with it ReadMasks[n].
I know I can do:
Code:
reg [7:0] ReadMasks[0:`REG_NUMBEROFREGISTERS];
always @ (posedge clk) begin
if (!nReset) begin
// initialize ReadMasks here without knowing in advance the number of registers and
// use masks that have been `defined
end
endThanks!
- - - Updated - - -
OK, after some thinking I came up with this:
Code:
reg [(8 * `REG_NUMBEROFREGISTERS) - 1:0] Registers;
reg [(8 * `REG_NUMBEROFREGISTERS) - 1:0] ReadMasks;
...
ReadMasks <= `REG_READMASKS;in the header file:
Code:
`define REG_NUMBEROFREGISTERS 4
`define REG_READMASKS 32'h0055AA1FComments welcome.